LCDs (Liquid Crystal Displays) have been known as one type of display devices. In particular, a liquid crystal display of a thin film transistor driven type (TFT-LCDs), which uses Thin Film Transistors (TFTs) for selecting displaying pixel elements, have been known as one type of LCDs. In the thin film transistor, an amorphous silicon (a-Si) semiconductor thin film or a polycrystalline silicon (p-Si) semiconductor thin film is used as a base material (active layer), and a channel portion and source/drain portions are formed in the active layer.
In a liquid crystal panel of an active matrix type, TFTs serving as switches for image signals are provided for the displaying pixel elements, and through switching operations of these TFTs, drive voltages of the displaying pixel elements are held. Thus, the active matrix type liquid crystal panel are excellent in image quality such as contrast, and response speeds, and therefore are widely used as monitors for a personal computer of portable type and desktop type as well as a projection monitor for displaying still and motion pictures.
In each of pixels of the display device of the active matrix type, a data-holding capacitance element (capacitance element for holding data) holds an image signal applied via the TFT. The displaying pixel element is driven in accordance with the voltage held by the capacitance element.
In the display device, displaying pixels are arranged in rows and columns, and gate lines (scanning lines) are arranged corresponding to the respective rows of the pixels. By sequentially driving the scanning lines to the selected state, the TFTs connected to a selected gate line are turned on so that the image signals are transferred to and held in the corresponding data-holding capacitance elements. As a sequence of driving the gate lines (scanning lines), there are an interlace system of sequentially driving alternate scanning lines to the selected state and a non-interlace system of sequentially driving the successive gate lines to the selected state. In any of these driving systems, for each pixel, there is required a time period in which all the gate lines (scanning lines) are once driven to the selected state after an image signal is once written before a next image signal is written into. An entire of the gate lines (scanning lines) forms one frame. Therefore, each displaying pixel element is required to hold the received image signal by the data-holding capacitance element for duration of one frame period. Usually, one frame cycle (frame frequency) is provided by 60 hertz (Hz). Therefore, rewriting of the holding voltage is performed in each unit pixel element for each one-frame period PF (= 1/60 second). During this frame period of time, the voltage on a pixel electrode node (voltage holding node) lowers only slightly, so that a change in reflectance (luminance) of the liquid crystal element of the pixel is small, and flicker, reduction in contrast and reduction in display quality are sufficiently suppressed.
In the liquid crystal display device, the current is mainly consumed for charging and discharging capacitances at crossings between scanning lines and data signal lines as well as capacitances of liquid crystal between the interconnection lines (scanning lines and data signal lines) and counter electrodes formed on a whole surface of the opposing substrate. A vertical scanning circuit driving the scanning lines to the selected state operates at a frequency equal to (frame frequency)×(number of scanning lines). Also, a horizontal scanning circuit writing image signal data onto data signal lines operates at a frequency equal to (frame frequency)×(number of scanning lines)×(number of data signal lines). Accordingly, charging and discharging of the inter-line capacitances as well as the capacitances between the interconnecting lines and the counter electrodes are performed at the operation frequencies of these vertical scanning circuit and the horizontal scanning circuit so that power consumption is increased.
For reducing the power consumption, it may be effective to lower the operation frequency, or to perform intermittently the vertical scanning and horizontal scanning. However, if the operation frequencies of the horizontal and vertical scanning circuits are lowered, a data rewriting period increases, and the voltage lowering at the pixel electrode node (voltage holding node) due to a leakage current significantly becomes large so that a reflectance (luminance) of the displaying pixel element accordingly changes significantly. Therefore, the voltage lowering of the pixel electrode node is observed as a flicker on a display screen, which degrades the display image quality. In addition, an average voltage applied to the liquid crystal element lowers so that good contrast cannot be achieved. Further, a display response speed lowers due to slow rewriting. These factors result in degraded display quality.
Japanese Patent Laying-Open No. 2000-356974 discloses an arrangement for preventing the voltage lowering due to the leakage current at the pixel electrode nodes of the display pixels, in which cross coupled type sense amplifiers formed of MOS transistors (insulated-gate field-effect transistors) are provided corresponding to the respective data lines to write inverted output signals of the output signals of the sense amplifiers into original displaying pixel elements.
In this prior art, when only holding of data is to be performed, the gate lines are sequentially selected to read pixel electrode signals of display pixels into the sense amplifiers, and inverted data of the sense amplifiers are re-stored on electrode nodes of original pixel elements. In the device in which the displaying pixel elements are formed of liquid crystal elements, storage of inverted image signals is performed for holding the image signals by application of AC voltages to the liquid crystal layers.
This prior art intends to reduce the power dissipation by restoring the held voltages of the respective pixel internally to eliminate the necessity for writing data from an external memory to restore (refresh) the accumulated voltages of the displaying pixel elements.
In the display device, for MOS transistors (insulated-gate field-effect transistors), generally low-temperature polycrystalline silicon TFTs are employed for ensuring reliability of a glass substrate or an insulating resin substrate for forming pixels. For the low-temperature polycrystalline silicon TFTs, impurity diffusion and other processes are performed through low-temperature processing. As compared with bulk type MOS transistors formed on a surface of a semiconductor substrate region, therefore, impurity diffusion is not sufficient, and a film quality of the polycrystalline silicon is low either. Further, the gate insulating film is not heat-processed or annealed at a sufficiently high temperature so that the film quality thereof is low. In the case of the TFT, a channel region is formed of a semiconductor layer formed on a glass substrate or an insulating resin substrate, and implantation of impurity ions for controlling a threshold voltage is not performed. Further, no bias voltage is applied to the substrate region.
For these factors, variations in threshold voltage of TFTs in display devices are larger than in bulk type MOS transistors. In the structure employing sense amplifier circuits for restoring (refreshing) the held voltage of the pixels, the sense amplifiers are arranged corresponding to the display pixel matrix, and therefore, it is required to use low-temperature TFTs for the components of the sense amplifier circuits. Such sense amplifier circuits accompany the problem that variations in threshold voltage of the TFTs are large and therefore accurate sensing operation cannot be achieved. Specifically, such sense amplifier circuit is formed of cross-coupled TFTs, and input signals undergo offset when the cross-coupled TFTs have different threshold voltages, so that the sense amplifier circuit cannot accurately amplify the data.
In particular, the held voltage in the pixel is merely held by a data-holding capacitance element in the pixel element, and a read voltage to the sense amplifier circuit is small. Therefore, when the input signals undergo the offset due to large variation in threshold voltages as described above, the sense amplifier circuit cannot accurately amplify the pixel voltage read from the pixel element, and the held voltage of the pixel cannot be refreshed.
Japanese Patent Laying-Open Nos. 20001-292041 and H9-320291 disclose the structures for reducing an offset in an operational amplifier of a sample/hold circuit arranged at an output of a horizontal drive circuit driving data lines in image display devices. These prior arts disclose the arrangements for reducing an adverse influence by the offset of the operational amplifier to incoming image signal, in which an output signal of the operational amplifier is fed back to bias a comparison reference voltage to cancel the offset of the operational amplifier. In these prior arts, however, consideration is given only to a configuration of a data line drive circuit for writing data into pixels in accordance with image data, and no consideration is given to such a problem of the lowering of held voltages in the pixels due to leakage current.
In addition, a test must be performed for determining whether each pixel can accurately perform a display operation after completion of the manufacturing process. In testing, test pixel data is written into each pixel, and then the pixel data thus written are read externally for comparison with the test data. In this test, it is therefore necessary to amplify accurately a minute voltage read from the pixel and to read the amplified voltage externally. For this, a tester is required to detect the minute pixel voltage, and thus becomes expensive.